PAE implies CX8, write readable code.
Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org>
---
arch/x86/include/asm/pgtable-3level.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -2,8 +2,6 @@
#ifndef _ASM_X86_PGTABLE_3LEVEL_H
#define _ASM_X86_PGTABLE_3LEVEL_H
-#include <asm/atomic64_32.h>
-
/*
* Intel Physical Address Extension (PAE) Mode - three-level page
* tables on PPro+ CPUs.
@@ -96,11 +94,13 @@ static inline void pud_clear(pud_t *pudp
#ifdef CONFIG_SMP
static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
{
- pte_t res;
+ pte_t old;
- res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
+ do {
+ old = *ptep;
+ } while (cmpxchg64(&ptep->pte, old.pte, 0ULL) != old.pte);
- return res;
+ return old;
}
#else
#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
