>-----Original Message----- >From: Andy Shevchenko <[email protected]> >Sent: Wednesday, December 2, 2020 10:35 PM >To: Ulf Hansson <[email protected]> >Cc: Shevchenko, Andriy <[email protected]>; Linus Walleij ><[email protected]>; Zulkifli, Muhammad Husaini ><[email protected]>; Hunter, Adrian ><[email protected]>; Michal Simek <[email protected]>; linux- >[email protected]; Linux ARM <[email protected]>; >Linux Kernel Mailing List <[email protected]>; Raja Subramanian, >Lakshmi Bai <[email protected]>; Wan Mohamad, >Wan Ahmad Zainie <[email protected]>; Mark >Gross <[email protected]> >Subject: Re: [PATCH v6 0/4] mmc: sdhci-of-arasan: Enable UHS-1 support for >Keem Bay SOC > >On Wed, Dec 2, 2020 at 4:10 PM Ulf Hansson <[email protected]> >wrote: >> On Wed, 2 Dec 2020 at 14:09, Andy Shevchenko ><[email protected]> wrote: >> > On Wed, Dec 2, 2020 at 2:44 PM Ulf Hansson <[email protected]> >wrote: > >... > >> > My point is that it may be *not* a pin control at all. >> >> Sorry, but I don't quite follow, what is *not* a pinctrl? >> >> According to the information I have received from the previous >> discussions [1], it's clear to me that the ARM SMC call ends up >> changing settings for the I/O-pads. Or did I get that wrong? > >I'm discussing the possible implication of the solution (faking pin >control) you are proposing. >In this case we know that it's a pin control *under the hood of IPC* >(!) but in another hardware generation it may be, for example,custom voltage >regulator. > >What you are proposing seems to me suboptimal and actually lying about >hardware. Because we do not have direct access to control this pad. >What we have is an IPC to firmware. And it's not our business what is under >the hood. > >It seems it was a mistake to talk about these details in the first place >because >it brings more confusion about hardware. So, consider that it's not a pin >control from OS perspective, but a firmware magic.
Maybe there is some misunderstanding regarding my statement in previous discussion. I quoted "IO Pad" based on the statement in Databook CFG[1][10:7] for AON register. From the Databook itself with additional confirmation from Keem Bay HW SOC Design Architect, there is no direct control of these AON register bits from GPIO pads. > >-- >With Best Regards, >Andy Shevchenko
