Hi, Dear maintainers, > A bus lock [1] is acquired through either split locked access to writeback > (WB) > memory or any locked access to non-WB memory. This is typically >1000 > cycles slower than an atomic operation within a cache line. It also disrupts > performance on other cores.
... > Change Log: > v4: > - Fix a ratelimit wording issue in the doc (Randy). > - Patch 4 is acked by Randy (Randy). Friendly reminder about this series... Thank you very much in advance for your time! -Fenghua
