On Fri, Dec 04, 2020 at 02:48:26PM +0100, Steen Hegelund wrote: > On 03.12.2020 22:52, Andrew Lunn wrote: > > What i have not yet seen is how this code plugs together with > > phylink_pcs_ops? > > > > Can this hardware also be used for SATA, USB? As far as i understand, > > the Marvell Comphy is multi-purpose, it is used for networking, USB, > > and SATA, etc. Making it a generic PHY then makes sense, because > > different subsystems need to use it. > > > > But it looks like this is for networking only? So i'm wondering if it > > belongs in driver/net/pcs and it should be accessed using > > phylink_pcs_ops? > > > > Andrew > > This is a PHY that communicates on a SerDes link to an ethernet PHY or a > SFP. So I took the lead from earlier work: the Microsemi Ocelot SerDes driver, > and added the Sparx5 SerDes PHY driver here since it is very similar in > intent. > It is not an ethernet PHY as such.
Okay, that is the normal situation in real hardware: MAC <---> PCS PHY <---> SerDes PHY <---> SerDes lanes where the PCS PHY handles the protocol level, and the SerDes PHY handles the clocking and electrical characteristics of the SerDes lanes. Maybe we should ask for a diagram of the setups when new support is submitted to make the process of understanding the hardware easier? -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!