On Wed, Dec 09, 2020 at 02:09:21PM +0530, Srikar Dronamraju wrote: > * Gautham R Shenoy <[email protected]> [2020-12-08 23:26:47]: > > > > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will > > > not > > > be released. Is this as expected? > > > > cacheinfo populates the cache->shared_cpu_map on the basis of which > > CPUs share the common device-tree node for a particular cache. There > > is one l1-cache object in the device-tree for a CPU node corresponding > > to a big-core. That the L1 is further split between the threads of the > > core is shown using ibm,thread-groups. > > > > Yes. > > > The ideal thing would be to add a "group_leader" field to "struct > > cache" so that we can create separate cache objects , one per thread > > group. I will take a stab at this in the v2. > > > > I am not saying this needs to be done immediately. We could add a TODO and > get it done later. Your patch is not making it worse. Its just that there is > still something more left to be done.
Yeah, it needs to be fixed but it may not be a 5.11 target. For now I will fix this patch to take care of the build errors on !PPC64 !SMT configs. I will post a separate series for making cacheinfo.c aware of thread-groups at the time of construction of the cache-chain. > > -- > Thanks and Regards > Srikar Dronamraju
