The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: b307ee828f61bc65d918e820a93b5c547a73dda3 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/b307ee828f61bc65d918e820a93b5c547a73dda3 Author: Gregory CLEMENT <[email protected]> AuthorDate: Wed, 25 Nov 2020 11:32:02 +01:00 Committer: Marc Zyngier <[email protected]> CommitterDate: Fri, 11 Dec 2020 14:47:49 dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Add the Device Tree binding documentation for the Microsemi Jaguar2, Luton and Serval interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] --- Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml index be82920..27b798b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -21,7 +21,11 @@ properties: compatible: items: - enum: + - mscc,jaguar2-icpu-intr + - mscc,luton-icpu-intr - mscc,ocelot-icpu-intr + - mscc,serval-icpu-intr + '#interrupt-cells': const: 1
