Quoting Alexandru Ardelean (2020-12-02 23:40:36) > Up until the these limits were global/hard-coded, since they are typically > limits of the fabric. > > However, since this is an FPGA generated clock, this may run on setups > where one clock is on a fabric, and another one synthesized on another > fabric connected via PCIe (or some other inter-connect, and then these > limits need to be adjusted for each instance of the AXI CLKGEN. > > This change wraps the current constants in 'axi_clkgen_limits' struct and > the 'axi_clkgen' instance keeps a copy of these limits, which is > initialized at probe from the default limits. > > The limits are stored on the device-tree OF table, so that we can adjust > them via the compatible string. > > Signed-off-by: Alexandru Ardelean <alexandru.ardel...@analog.com> > ---
Applied to clk-next
