[PATCH 2/5] clk: renesas: r8a779a0: Add RWDT clocks

[Wolfram Sang]

And introduce critical clocks, too, because RWDT is one.

Signed-off-by: Wolfram Sang <wsa+rene...@sang-engineering.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c 
b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index aa5389b04d74..bf9fdcdd7d85 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -188,6 +188,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] 
__initconst = {
        DEF_MOD("vin35",        827,    R8A779A0_CLK_S1D1),
        DEF_MOD("vin36",        828,    R8A779A0_CLK_S1D1),
        DEF_MOD("vin37",        829,    R8A779A0_CLK_S1D1),
+       DEF_MOD("rwdt",         907,    R8A779A0_CLK_R),
 };
 
 static spinlock_t cpg_lock;
@@ -261,6 +262,10 @@ static struct clk * __init 
rcar_r8a779a0_cpg_clk_register(struct device *dev,
                                         __clk_get_name(parent), 0, mult, div);
 }
 
+static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
+       MOD_CLK_ID(907),        /* RWDT */
+};
+
 /*
  * CPG Clock Data
  */
@@ -311,6 +316,10 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info 
__initconst = {
        .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
        .num_hw_mod_clks = 15 * 32,
 
+       /* Critical Module Clocks */
+       .crit_mod_clks          = r8a779a0_crit_mod_clks,
+       .num_crit_mod_clks      = ARRAY_SIZE(r8a779a0_crit_mod_clks),
+
        /* Callbacks */
        .init = r8a779a0_cpg_mssr_init,
        .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
-- 
2.29.2