[PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

[Konrad Dybcio]

Using this code on A5xx (and probably older too) causes a
smmu bug.

Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
Signed-off-by: Konrad Dybcio <konrad.dyb...@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delre...@somainline.org>
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++++++++---------
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +++++
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 6cf9975e951e..f09175698827 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
                struct platform_device *pdev)
 {
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-       struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
-       struct io_pgtable_domain_attr pgtbl_cfg;
        struct iommu_domain *iommu;
        struct msm_mmu *mmu;
        struct msm_gem_address_space *aspace;
@@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
        if (!iommu)
                return NULL;
 
-       /*
-        * This allows GPU to set the bus attributes required to use system
-        * cache on behalf of the iommu page table walker.
-        */
-       if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
-               pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
-               iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, 
&pgtbl_cfg);
+
+       if (adreno_is_a6xx(adreno_gpu)) {
+               struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+               struct io_pgtable_domain_attr pgtbl_cfg;
+               /*
+               * This allows GPU to set the bus attributes required to use 
system
+               * cache on behalf of the iommu page table walker.
+               */
+               if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
+                       pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
+                       iommu_domain_set_attr(iommu, 
DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
+               }
        }
 
        mmu = msm_iommu_new(&pdev->dev, iommu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 4574d85c5680..08421fa54a50 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -226,6 +226,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
        return gpu->revn == 540;
 }
 
+static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
+{
+       return ((gpu->revn < 700 && gpu->revn > 599));
+}
+
 static inline int adreno_is_a618(struct adreno_gpu *gpu)
 {
        return gpu->revn == 618;
-- 
2.29.2