On Tue, 2007-12-18 at 12:07 -0800, [EMAIL PROTECTED] wrote: > On Tue, Dec 18, 2007 at 05:50:42PM +0100, Stefan Richter wrote: > > > Do I understand correctly?: A device and the CPUs communicate via two > > separate memory areas: A data buffer and a status FIFO. The NUMA > > interconnect may reorder accesses of the device to the areas. (Write > > accesses? Read accesses? Both?) > > Yes, I think you understand. Reorderings are possible on reads and > writes. Things get synced up by either an interrupt or a write to > a memory region with a "barrier attribute". Memory allocated with > dma_alloc_coherent() gets the barrier attribute. The idea here is > to allow memory allocated with plain old malloc() or whatever to > get the same attribute. > > > > > To ensure synchronization between device and CPUs, you want to mark a > > memory area which is to be dma-mapped with a flag which says: "Writes > > to the memory region will cause in-flight DMA to be flushed". Whose > > writes? A write access from the device or a write access from a CPU? > > A write from the device, e.g., when the device writes to indicate > "data DMA is complete".
Can't you just have a primitive to sync things up that you call explicitely from your driver after fetching a new status entry ? Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/