On Thu, Dec 24, 2020 at 05:12:47PM +0530, Kishon Vijay Abraham I wrote: > AM64 has a single lane SERDES which can be configured to be used > with either PCIe or USB. Define the possilbe values for the SERDES > function in AM64 SoC here.
Doesn't look like this is used? Would the common phy modes work? > > Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com> > --- > include/dt-bindings/mux/ti-serdes.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/dt-bindings/mux/ti-serdes.h > b/include/dt-bindings/mux/ti-serdes.h > index 9047ec6bd3cf..68e0f76deed1 100644 > --- a/include/dt-bindings/mux/ti-serdes.h > +++ b/include/dt-bindings/mux/ti-serdes.h > @@ -90,4 +90,8 @@ > #define J7200_SERDES0_LANE3_USB 0x2 > #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 > > +/* AM64 */ > +#define AM64_SERDES0_LANE0_PCIE0 0x0 > +#define AM64_SERDES0_LANE0_USB 0x1 > + > #endif /* _DT_BINDINGS_MUX_TI_SERDES */ > -- > 2.17.1 >
