On 12/01/2021 01:35, Kuninori Morimoto wrote:
Hi Richard
Some codecs need plls and/or sysclks to be configured using the
snd_soc_component_set_[sysclk|pll] functions. These drivers cannot
necessarily be converted to use the clock framework. If the codec is on
a I2C/SPI bus, a nested clk_get would be needed to enable the bus clock.
But the clock framework does not support nested operations and this would
deadlock.
This patch adds new dt properties that list phandles of components with
the pll/sysclk settings to be applied. Multiple settings can be given for
the same phandle to allow for components with multiple clocks and plls.
The plls and sysclks are enabled when the card bias level moves to STANDBY
and disabled when it moves to OFF.
The implementation does not attempt to handle specifying complex clock
ordering interdependencies between components. The plls and sysclks are
applied to a component as it is passed to the card set_bias_level/
set_bias_level_post callbacks. It follows from this that the order
components are configured is the order that they are passed to those
callbacks.
Signed-off-by: Richard Fitzgerald <r...@opensource.cirrus.com>
---
As I mentioned in v3, adding *general* pll to common card driver is
maybe difficult.
You did say that. But you did not say why.
Can you be more specific about what problem you see with adding it
to the generic driver?
Using your own customized audio-graph-card driver is better idea,
instead of adding code to common driver.
I just don't want to duplicate code without good reason.
I think Sameer's Tegra driver (= [3/6]) is good sample for you ?
https://lore.kernel.org/r/1606413823-19885-1-git-send-email-spu...@nvidia.com
Thank you for your help !!
Best regards
---
Kuninori Morimoto
