A title markup length is smaller than required;
A literal block is not marked as such.
This fixes the warnings below:
.../Documentation/fpga/dfl.rst:505: WARNING: Title underline too short.
Location of DFLs on a PCI Device
===========================
.../Documentation/fpga/dfl.rst:523: WARNING: Unexpected indentation.
.../Documentation/fpga/dfl.rst:523: WARNING: Blank line required after
table.
.../Documentation/fpga/dfl.rst:524: WARNING: Block quote ends without a
blank line; unexpected unindent.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
Documentation/fpga/dfl.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index ea8cefc18bdb..716a3d705046 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -502,7 +502,7 @@ FME Partial Reconfiguration Sub Feature driver (see
drivers/fpga/dfl-fme-pr.c)
could be a reference.
Location of DFLs on a PCI Device
-===========================
+================================
The original method for finding a DFL on a PCI device assumed the start of the
first DFL to offset 0 of bar 0. If the first node of the DFL is an FME,
then further DFLs in the port(s) are specified in FME header registers.
@@ -513,7 +513,7 @@ VSEC ID of 0x43 for this purpose. The vendor specific
data begins with a 4 byte vendor specific register for the number of DFLs
followed 4 byte
Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR
register
indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0
are
-zero.
+zero::
+----------------------------+
|31 Number of DFLS 0|
--
2.29.2
