On Thu, Jan 14, 2021 at 3:13 PM AngeloGioacchino Del Regno <angelogioacchino.delre...@somainline.org> wrote: > > Il 14/01/21 23:12, Jeffrey Hugo ha scritto: > > On Sat, Jan 9, 2021 at 6:47 AM AngeloGioacchino Del Regno > > <angelogioacchino.delre...@somainline.org> wrote: > >> > >> This clock enables the GPLL0 output to the multimedia subsystem > >> clock controller. > >> > >> Signed-off-by: AngeloGioacchino Del Regno > >> <angelogioacchino.delre...@somainline.org> > > > > Any reason why you are not also adding the div_clk? > > > > Yes, just one: I haven't tested it... and my devices worked without. > Perhaps we can add it whenever we find out if something really needs it?
I'm mildly surprised you need to turn on the gate to the PLL0 out, but not the div_out. The div_out/div_clk is also fed into every RCG that exists in the MMCC. Per the frequency plan the following RCGs require it - cci cpp fd_core camss_gp[0-1] jpeg0 mclk[0-3] csi[0-2]phytimer dp_gtc maxi axi ahb Also, I'm very interested in all things 8998, and would generally appreciate being added to the to: list.
