On Fri, Jan 15, 2021 at 12:17:01PM -0300, Arnaldo Carvalho de Melo wrote: [...]
> > > Thanks for the review, Jiri. > > > > > > Note, after testing with Arm SPE, we found the store operations don't > > > contain the information for L1 cache hit or miss, this leads to there > > > have no statistics for "st_l1hit" and "st_l1miss"; finally the single > > > cache line view only can show the load samples and fails to show store > > > opreations due to the empty statistics for "st_l1hit" and "st_l1miss". > > > > > > This is related the hardware issue, after some discussion internally, > > > so far cannot find a easy way to set memory flag for L1 cache hit or > > > miss for store operations (more specific, set flags PERF_MEM_LVL_HIT or > > > PERF_MEM_LVL_MISS for store's L1 cache accessing). > > > > > > Given it is uncertain for this issue, please hold on for this patch > > > series and I will resend if have any conclusion. > > > > > > And really sorry I notify this too late. > > > > no problem, I think we can take some of the refactoring patches anyway > > Agreed, in fact I already processed this series in my local branch and > I'm test building everything now. Thanks a lot, Arnalod. Just remind in case you miss the latest series due to the flood emails, I have extracted and refined the refactoring patches, and have sent out patch series v4 [1] for picking up (and have received ACK tags from Namhyung and Jiri). Leo
