> -----Original Message-----
> From: Peter Zijlstra <pet...@infradead.org>
> Sent: Saturday, January 16, 2021 4:03 AM
> To: Zhang, Rui <rui.zh...@intel.com>
> Cc: mi...@redhat.com; a...@kernel.org; mark.rutl...@arm.com;
> alexander.shish...@linux.intel.com; jo...@redhat.com;
> namhy...@kernel.org; linux-kernel@vger.kernel.org; x...@kernel.org;
> kan.li...@linux.intel.com; a...@linux.intel.com
> Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
> Importance: High
>
> On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote:
> > In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the
> > energy counter, and the higher 32bits are reserved.
> >
> > Add the MSR mask for these MSRs to fix a problem that the RAPL PMU
> > events are added erroneously when higher 32bits contain non-zero value.
>
> Why would these high bits be non-zero?
On SPR platform, the high bits of Psys energy counter are reused for other
purpose.
High bits for other RAPL domains energy counters still return 0.
I didn't mention this because I thought this patch should be okay as a generic
fix.
Thanks,
rui
