On 14-01-21, 18:47, AngeloGioacchino Del Regno wrote: > The TCSR's PHY_CLK_SCHEME register is not available on all SoC > models, but some may still use a differential reference clock. > > In preparation for these SoCs, add a se_clk_scheme_default > configuration entry and declare it to true for all currently > supported SoCs (retaining the previous defaults. > > This patch brings no functional changes.
Patch 2 had two blank lines getting inserted, I have fixed that up while applying.. so: Applied all, thanks -- ~Vinod
