And remove an incorrect entry.
Fixes the following W=1 kernel build warning(s):
drivers/clk/st/clkgen-pll.c:142: warning: cannot understand function
prototype: 'struct clkgen_pll '
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Stephen Boyd <sb...@kernel.org>
Cc: Stephen Gallimore <stephen.gallim...@st.com>
Cc: Pankaj Dev <pankaj....@st.com>
Cc: linux-...@vger.kernel.org
Signed-off-by: Lee Jones <lee.jo...@linaro.org>
---
drivers/clk/st/clkgen-pll.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index c3952f2c42ba2..119c5b33080cf 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -130,12 +130,11 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
* parent - fixed parent. No clk_set_parent support
*/
-/**
+/*
* PLL clock that is integrated in the ClockGenA instances on the STiH415
* and STiH416.
*
* @hw: handle between common and hardware-specific interfaces.
- * @type: PLL instance type.
* @regs_base: base of the PLL configuration register(s).
*
*/
--
2.25.1
