Lu Baolu <baolu...@linux.intel.com> writes:

> This adds a new trace event to track the submissions of requests to the
> invalidation queue. This event will provide the information like:
> - IOMMU name
> - Invalidation type
> - Descriptor raw data
>
> A sample output like:
> | qi_submit: iotlb_inv dmar1: 0x100e2 0x0 0x0 0x0
> | qi_submit: dev_tlb_inv dmar1: 0x1000000003 0x7ffffffffffff001 0x0 0x0
> | qi_submit: iotlb_inv dmar2: 0x800f2 0xf9a00005 0x0 0x0
>
> This will be helpful for queued invalidation related debugging.
>
> Signed-off-by: Lu Baolu <baolu...@linux.intel.com>

While compiling current linux-next for some other test I noticed a
compiler error because of this patch:

drivers/iommu/intel/dmar.c: In function ‘qi_submit_sync’:
drivers/iommu/intel/dmar.c:1311:3: error: implicit declaration of function 
‘trace_qi_submit’ [-Werror=implicit-function-declaration]
 1311 |   trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,
      |   ^~~~~~~~~~~~~~~
cc1: some warnings being treated as errors

On my machine CONFIG_INTEL_IOMMU is not set so
#include <trace/events/intel_iommu.h> cannot provide the prototype for
that function.

Dirk

> ---
>  drivers/iommu/intel/dmar.c         |  3 +++
>  include/trace/events/intel_iommu.h | 37 ++++++++++++++++++++++++++++++
>  2 files changed, 40 insertions(+)
>
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> index 004feaed3c72..bd51f33642e0 100644
> --- a/drivers/iommu/intel/dmar.c
> +++ b/drivers/iommu/intel/dmar.c
> @@ -31,6 +31,7 @@
>  #include <linux/limits.h>
>  #include <asm/irq_remapping.h>
>  #include <asm/iommu_table.h>
> +#include <trace/events/intel_iommu.h>
>  
>  #include "../irq_remapping.h"
>  
> @@ -1307,6 +1308,8 @@ int qi_submit_sync(struct intel_iommu *iommu, struct 
> qi_desc *desc,
>               offset = ((index + i) % QI_LENGTH) << shift;
>               memcpy(qi->desc + offset, &desc[i], 1 << shift);
>               qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE;
> +             trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,
> +                             desc[i].qw2, desc[i].qw3);
>       }
>       qi->desc_status[wait_index] = QI_IN_USE;
>  
> diff --git a/include/trace/events/intel_iommu.h 
> b/include/trace/events/intel_iommu.h
> index 112bd06487bf..aad2ff0c1e2e 100644
> --- a/include/trace/events/intel_iommu.h
> +++ b/include/trace/events/intel_iommu.h
> @@ -135,6 +135,43 @@ DEFINE_EVENT(dma_map_sg, bounce_map_sg,
>                struct scatterlist *sg),
>       TP_ARGS(dev, index, total, sg)
>  );
> +
> +TRACE_EVENT(qi_submit,
> +     TP_PROTO(struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3),
> +
> +     TP_ARGS(iommu, qw0, qw1, qw2, qw3),
> +
> +     TP_STRUCT__entry(
> +             __field(u64, qw0)
> +             __field(u64, qw1)
> +             __field(u64, qw2)
> +             __field(u64, qw3)
> +             __string(iommu, iommu->name)
> +     ),
> +
> +     TP_fast_assign(
> +             __assign_str(iommu, iommu->name);
> +             __entry->qw0 = qw0;
> +             __entry->qw1 = qw1;
> +             __entry->qw2 = qw2;
> +             __entry->qw3 = qw3;
> +     ),
> +
> +     TP_printk("%s %s: 0x%llx 0x%llx 0x%llx 0x%llx",
> +               __print_symbolic(__entry->qw0 & 0xf,
> +                                { QI_CC_TYPE,        "cc_inv" },
> +                                { QI_IOTLB_TYPE,     "iotlb_inv" },
> +                                { QI_DIOTLB_TYPE,    "dev_tlb_inv" },
> +                                { QI_IEC_TYPE,       "iec_inv" },
> +                                { QI_IWD_TYPE,       "inv_wait" },
> +                                { QI_EIOTLB_TYPE,    "p_iotlb_inv" },
> +                                { QI_PC_TYPE,        "pc_inv" },
> +                                { QI_DEIOTLB_TYPE,   "p_dev_tlb_inv" },
> +                                { QI_PGRP_RESP_TYPE, "page_grp_resp" }),
> +             __get_str(iommu),
> +             __entry->qw0, __entry->qw1, __entry->qw2, __entry->qw3
> +     )
> +);
>  #endif /* _TRACE_INTEL_IOMMU_H */
>  
>  /* This part must be outside protection */

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