On 24/12/2020 01:48, Yongqiang Niu wrote: > Add documentation for the mt8192 gce. > > Add gce header file defined the gce hardware event, > subsys number and constant for mt8192. > > Signed-off-by: Yongqiang Niu <yongqiang....@mediatek.com> > --- > .../devicetree/bindings/mailbox/mtk-gce.txt | 7 +- > include/dt-bindings/gce/mt8192-gce.h | 419 > +++++++++++++++++++++ > 2 files changed, 423 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/gce/mt8192-gce.h > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > index cf48cd8..f48ae45 100644 > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > @@ -9,8 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please > refer to > mailbox.txt for generic information about mailbox device-tree bindings. > > Required properties: > -- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or > - "mediatek,mt6779-gce". > +- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce", > + "mediatek,mt8192-gce" or "mediatek,mt6779-gce". > - reg: Address range of the GCE unit > - interrupts: The interrupt signal from the GCE block > - clock: Clocks according to the common clock binding > @@ -36,7 +36,8 @@ Optional properties for a client device: > size: the total size of register address that GCE can access. > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', > -'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as > +'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h' or > +'dt-bindings/gce/mt6779-gce.h'. Such as > sub-system ids, thread priority, event ids. > > Example: > diff --git a/include/dt-bindings/gce/mt8192-gce.h > b/include/dt-bindings/gce/mt8192-gce.h > new file mode 100644 > index 0000000..0627544 > --- /dev/null > +++ b/include/dt-bindings/gce/mt8192-gce.h > @@ -0,0 +1,419 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2020 MediaTek Inc. > + * Author: Yongqiang Niu <yongqiang....@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_GCE_MT8192_H > +#define _DT_BINDINGS_GCE_MT8192_H > + > +/* assign timeout 0 also means default */ > +#define CMDQ_NO_TIMEOUT 0xffffffff > +#define CMDQ_TIMEOUT_DEFAULT 1000 > + > +/* GCE thread priority */ > +#define CMDQ_THR_PRIO_LOWEST 0 > +#define CMDQ_THR_PRIO_1 1 > +#define CMDQ_THR_PRIO_2 2 > +#define CMDQ_THR_PRIO_3 3 > +#define CMDQ_THR_PRIO_4 4 > +#define CMDQ_THR_PRIO_5 5 > +#define CMDQ_THR_PRIO_6 6 > +#define CMDQ_THR_PRIO_HIGHEST 7 > + > +/* CPR count in 32bit register */ > +#define GCE_CPR_COUNT 1312 > + > +/* GCE subsys table */ > +#define SUBSYS_1300XXXX 0 > +#define SUBSYS_1400XXXX 1 > +#define SUBSYS_1401XXXX 2 > +#define SUBSYS_1402XXXX 3 > +#define SUBSYS_1502XXXX 4 > +#define SUBSYS_1880XXXX 5 > +#define SUBSYS_1881XXXX 6 > +#define SUBSYS_1882XXXX 7 > +#define SUBSYS_1883XXXX 8 > +#define SUBSYS_1884XXXX 9 > +#define SUBSYS_1000XXXX 10 > +#define SUBSYS_1001XXXX 11 > +#define SUBSYS_1002XXXX 12 > +#define SUBSYS_1003XXXX 13 > +#define SUBSYS_1004XXXX 14 > +#define SUBSYS_1005XXXX 15 > +#define SUBSYS_1020XXXX 16 > +#define SUBSYS_1028XXXX 17 > +#define SUBSYS_1700XXXX 18 > +#define SUBSYS_1701XXXX 19 > +#define SUBSYS_1702XXXX 20 > +#define SUBSYS_1703XXXX 21 > +#define SUBSYS_1800XXXX 22 > +#define SUBSYS_1801XXXX 23 > +#define SUBSYS_1802XXXX 24 > +#define SUBSYS_1804XXXX 25 > +#define SUBSYS_1805XXXX 26 > +#define SUBSYS_1808XXXX 27 > +#define SUBSYS_180aXXXX 28 > +#define SUBSYS_180bXXXX 29 > +#define SUBSYS_NO_SUPPORT 99 How will we you SUBSYS_NO_SUPPORT? > + > +/* GCE General Purpose Register (GPR) support > + * Leave note for scenario usage here > + */ > +/* GCE: write mask */ > +#define GCE_GPR_R00 0x00 What are these defines for? Regards, Matthias > +#define GCE_GPR_R01 0x01 > +/* MDP: P1: JPEG dest */ > +#define GCE_GPR_R02 0x02 > +#define GCE_GPR_R03 0x03 > +/* MDP: PQ color */ > +#define GCE_GPR_R04 0x04 > +/* MDP: 2D sharpness */ > +#define GCE_GPR_R05 0x05 > +/* DISP: poll esd */ > +#define GCE_GPR_R06 0x06 > +#define GCE_GPR_R07 0x07 > +/* MDP: P4: 2D sharpness dst */ > +#define GCE_GPR_R08 0x08 > +#define GCE_GPR_R09 0x09 > +/* VCU: poll with timeout for GPR timer */ > +#define GCE_GPR_R10 0x0A > +#define GCE_GPR_R11 0x0B > +/* CMDQ: debug */ > +#define GCE_GPR_R12 0x0C > +#define GCE_GPR_R13 0x0D > +/* CMDQ: P7: debug */ > +#define GCE_GPR_R14 0x0E > +#define GCE_GPR_R15 0x0F > +
