On Sat, Jan 30, 2021 at 4:16 PM Nadav Amit <nadav.a...@gmail.com> wrote:
>
> From: Nadav Amit <na...@vmware.com>
>
> x86 currently has a TLB-generation tracking logic that can be used by
> additional architectures (as long as they implement some additional
> logic).
>
> Extract the relevant pieces of code from x86 to general TLB code. This
> would be useful to allow to write the next "fine granularity deferred
> TLB flushes detection" patches without making them x86-specific.
Tentative ACK.
My biggest concern about this is that, once it's exposed to core code,
people might come up with clever-but-incorrect ways to abuse it. Oh
well.
> struct workqueue_struct *efi_rts_wq;
> diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
> index 0974ad501a47..2035ac319c2b 100644
> --- a/include/linux/mm_types.h
> +++ b/include/linux/mm_types.h
> @@ -560,6 +560,17 @@ struct mm_struct {
>
> #ifdef CONFIG_IOMMU_SUPPORT
> u32 pasid;
> +#endif
> +#ifdef CONFIG_ARCH_HAS_TLB_GENERATIONS
> + /*
> + * Any code that needs to do any sort of TLB flushing for this
> + * mm will first make its changes to the page tables, then
> + * increment tlb_gen, then flush. This lets the low-level
> + * flushing code keep track of what needs flushing.
> + *
> + * This is not used on Xen PV.
That last comment should probably go away.
