[PATCH RFC 6/7] kvm: x86: Add AMX_TILE, AMX_INT8 and AMX_BF16 support

[Jing Liu]

Intel introduces AMX architecture in SPR platform, which includes
AMX_TILE, AMX_INT8 and AMX_BF16 support.

Exposes these features to KVM guest.

Signed-off-by: Jing Liu <jing2....@linux.intel.com>
---
 arch/x86/kvm/cpuid.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index ee1fac0a865e..1b3ea9195a75 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -423,7 +423,8 @@ void kvm_set_cpu_caps(void)
                F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
                F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
                F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
-               F(SERIALIZE) | F(TSXLDTRK)
+               F(SERIALIZE) | F(TSXLDTRK) |
+               F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)
        );
 
        /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
@@ -544,6 +545,8 @@ static struct kvm_cpuid_entry2 *do_host_cpuid(struct 
kvm_cpuid_array *array,
        case 0x14:
        case 0x17:
        case 0x18:
+       case 0x1d:
+       case 0x1e:
        case 0x1f:
        case 0x8000001d:
                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
@@ -667,6 +670,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array 
*array, u32 function)
                break;
        case 9:
                break;
+       case 0x1e:
+               break;
        case 0xa: { /* Architectural Performance Monitoring */
                struct x86_pmu_capability cap;
                union cpuid10_eax eax;
@@ -766,9 +771,12 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array 
*array, u32 function)
                        entry->edx = 0;
                }
                break;
+       /* Intel AMX TILE */
+       case 0x1d:
        /* Intel PT */
        case 0x14:
-               if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
+               if ((function == 0x14 && 
!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) ||
+                   (function == 0x1d && 
!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE))) {
                        entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
                        break;
                }
-- 
2.18.4