[PATCH v5 04/22] powerpc/32: Reorder instructions to avoid using CTR in syscall entry

[Christophe Leroy]

Now that we are using rfi instead of mtmsr to reactivate MMU, it is
possible to reorder instructions and avoid the need to use CTR for
stashing SRR0.

null_syscall on 8xx is reduced by 3 cycles (283 => 280 cycles).

Signed-off-by: Christophe Leroy <christophe.le...@csgroup.eu>
---
 arch/powerpc/kernel/head_32.h | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
index 4029c51dce5d..24dc326e0d56 100644
--- a/arch/powerpc/kernel/head_32.h
+++ b/arch/powerpc/kernel/head_32.h
@@ -116,30 +116,28 @@
 .endm
 
 .macro SYSCALL_ENTRY trapno
-       mfspr   r12,SPRN_SPRG_THREAD
        mfspr   r9, SPRN_SRR1
-       mfspr   r11, SPRN_SRR0
-       mtctr   r11
+       mfspr   r10, SPRN_SRR0
        andi.   r11, r9, MSR_PR
+       beq-    99f
+       LOAD_REG_IMMEDIATE(r11, MSR_KERNEL)             /* can take exceptions 
*/
+       lis     r12, 1f@h
+       ori     r12, r12, 1f@l
+       mtspr   SPRN_SRR1, r11
+       mtspr   SPRN_SRR0, r12
+       mfspr   r12,SPRN_SPRG_THREAD
        mr      r11, r1
        lwz     r1,TASK_STACK-THREAD(r12)
-       beq-    99f
+       tovirt(r12, r12)
        addi    r1, r1, THREAD_SIZE - INT_FRAME_SIZE
-       LOAD_REG_IMMEDIATE(r10, MSR_KERNEL)             /* can take exceptions 
*/
-       mtspr   SPRN_SRR1, r10
-       lis     r10, 1f@h
-       ori     r10, r10, 1f@l
-       mtspr   SPRN_SRR0, r10
        rfi
 1:
-       tovirt(r12, r12)
        stw     r11,GPR1(r1)
        stw     r11,0(r1)
        mr      r11, r1
+       stw     r10,_NIP(r11)
        mflr    r10
        stw     r10, _LINK(r11)
-       mfctr   r10
-       stw     r10,_NIP(r11)
        mfcr    r10
        rlwinm  r10,r10,0,4,2   /* Clear SO bit in CR */
        stw     r10,_CCR(r11)           /* save registers */
-- 
2.25.0