Quoting JC Kuo (2021-01-19 23:34:02) > PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware > power sequencers' output to enable/disable PLLE. PLLE hardware power > sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers > are enabled. > > Signed-off-by: JC Kuo <jc...@nvidia.com> > Acked-by: Thierry Reding <tred...@nvidia.com> > ---
Acked-by: Stephen Boyd <sb...@kernel.org>
