Quoting Alexandru Ardelean (2021-02-01 07:12:42) > The intent is to be able to run this driver to access the IP core in setups > where FPGA board is also connected via a PCIe bus. In such cases the number > of combinations explodes, where the host system can be an x86 with Xilinx > Zynq/ZynqMP/Microblaze board connected via PCIe. > Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe. > > To accommodate for these cases, this change removes the limitation for this > driver to be compilable only on Zynq/Microblaze architectures. > And adds dependencies on the mechanisms required by the driver to work (OF > and HAS_IOMEM). > > Signed-off-by: Dragos Bogdan <dragos.bog...@analog.com> > Signed-off-by: Alexandru Ardelean <alexandru.ardel...@analog.com> > ---
Applied to clk-next
