[PATCH v2.1 2/3] objtool,x86: Additionally decode: mov %rsp, (%reg)

[Peter Zijlstra]

Subject: objtool,x86: Additionally decode: mov %rsp, (%reg)
From: Peter Zijlstra <pet...@infradead.org>
Date: Wed Feb 3 12:02:18 CET 2021

Where we already decode: mov %rsp, %reg, also decode mov %rsp, (%reg).

Nothing should match for this new stack-op.

Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org>
---
 tools/objtool/arch/x86/decode.c |   42 ++++++++++++++++++++++++++++++++--------
 1 file changed, 34 insertions(+), 8 deletions(-)

--- a/tools/objtool/arch/x86/decode.c
+++ b/tools/objtool/arch/x86/decode.c
@@ -222,15 +222,38 @@ int arch_decode_instruction(const struct
                break;
 
        case 0x89:
-               if (rex_w && !rex_r && modrm_mod == 3 && modrm_reg == 4) {
+               if (rex_w && !rex_r && modrm_reg == 4) {
 
-                       /* mov %rsp, reg */
-                       ADD_OP(op) {
-                               op->src.type = OP_SRC_REG;
-                               op->src.reg = CFI_SP;
-                               op->dest.type = OP_DEST_REG;
-                               op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
+                       if (modrm_mod == 3) {
+                               /* mov %rsp, reg */
+                               ADD_OP(op) {
+                                       op->src.type = OP_SRC_REG;
+                                       op->src.reg = CFI_SP;
+                                       op->dest.type = OP_DEST_REG;
+                                       op->dest.reg = 
op_to_cfi_reg[modrm_rm][rex_b];
+                               }
+                               break;
+
+                       } else {
+                               /* skip nontrivial SIB */
+                               if (modrm_rm == 4 && sib != 0x24)
+                                       break;
+
+                               /* skip RIP relative displacement */
+                               if (modrm_rm == 5 && modrm_mod == 0)
+                                       break;
+
+                               /* mov %rsp, disp(%reg) */
+                               ADD_OP(op) {
+                                       op->src.type = OP_SRC_REG;
+                                       op->src.reg = CFI_SP;
+                                       op->dest.type = OP_DEST_REG_INDIRECT;
+                                       op->dest.reg = 
op_to_cfi_reg[modrm_rm][rex_b];
+                                       op->dest.offset = 
insn.displacement.value;
+                               }
+                               break;
                        }
+
                        break;
                }
 
@@ -259,8 +282,10 @@ int arch_decode_instruction(const struct
                                op->dest.reg = CFI_BP;
                                op->dest.offset = insn.displacement.value;
                        }
+                       break;
+               }
 
-               } else if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
+               if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
 
                        /* mov reg, disp(%rsp) */
                        ADD_OP(op) {
@@ -270,6 +295,7 @@ int arch_decode_instruction(const struct
                                op->dest.reg = CFI_SP;
                                op->dest.offset = insn.displacement.value;
                        }
+                       break;
                }
 
                break;