On Wed, 27 Jan 2021 at 08:56, Anshuman Khandual <[email protected]> wrote: > > From: Suzuki K Poulose <[email protected]> > > CoreSight PMU supports aux-buffer for the ETM tracing. The trace > generated by the ETM (associated with individual CPUs, like Intel PT) > is captured by a separate IP (CoreSight TMC-ETR/ETF until now). > > The TMC-ETR applies formatting of the raw ETM trace data, as it > can collect traces from multiple ETMs, with the TraceID to indicate > the source of a given trace packet. > > Arm Trace Buffer Extension is new "sink" IP, attached to individual > CPUs and thus do not provide additional formatting, like TMC-ETR. > > Additionally, a system could have both TRBE *and* TMC-ETR for > the trace collection. e.g, TMC-ETR could be used as a single > trace buffer to collect data from multiple ETMs to correlate > the traces from different CPUs. It is possible to have a > perf session where some events end up collecting the trace > in TMC-ETR while the others in TRBE. Thus we need a way > to identify the type of the trace for each AUX record. > > Define the trace formats exported by the CoreSight PMU. > We don't define the flags following the "ETM" as this > information is available to the user when issuing > the session. What is missing is the additional > formatting applied by the "sink" which is decided > at the runtime and the user may not have a control on. > > So we define : > - CORESIGHT format (indicates the Frame format) > - RAW format (indicates the format of the source) > > The default value is CORESIGHT format for all the records > (i,e == 0). Add the RAW format for the TRBE sink driver. > > Cc: Peter Zijlstra <[email protected]> > Cc: Mike Leach <[email protected]> > Cc: Mathieu Poirier <[email protected]> > Cc: Leo Yan <[email protected]> > Cc: Anshuman Khandual <[email protected]> > Signed-off-by: Suzuki K Poulose <[email protected]> > Signed-off-by: Anshuman Khandual <[email protected]> > --- > drivers/hwtracing/coresight/coresight-trbe.c | 2 ++ > include/uapi/linux/perf_event.h | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c > b/drivers/hwtracing/coresight/coresight-trbe.c > index 1464d8b..7c0e691 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -511,6 +511,7 @@ static unsigned long arm_trbe_update_buffer(struct > coresight_device *csdev, > if (cpudata->mode != CS_MODE_PERF) > return -EINVAL; > > + perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW); > /* > * If the TRBE was disabled due to lack of space in the AUX buffer or > a > * spurious fault, the driver leaves it disabled, truncating the > buffer. > @@ -606,6 +607,7 @@ static void trbe_handle_overflow(struct > perf_output_handle *handle) > size = offset - PERF_IDX2OFF(handle->head, buf); > if (buf->snapshot) > handle->head = offset; > + perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW); > perf_aux_output_end(handle, size); > > event_data = perf_aux_output_begin(handle, event); > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index 9a5ca45..169e6b3 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -1111,6 +1111,10 @@ enum perf_callchain_context { > #define PERF_AUX_FLAG_COLLISION 0x08 /* sample > collided with another */ > #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace > format type */ > > +/* CoreSight PMU AUX buffer formats */ > +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for > backward compatibility */ > +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format > of the source */ > + > #define PERF_FLAG_FD_NO_GROUP (1UL << 0) > #define PERF_FLAG_FD_OUTPUT (1UL << 1) > #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu > mode only */ > -- > 2.7.4 >
Reviewed-by: Mike Leach <[email protected]> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
