On Tue, 16 Feb 2021 20:09:51 -0800 Ben Widawsky <ben.widaw...@intel.com> wrote:
> Provide enough functionality to utilize the mailbox of a memory device. > The mailbox is used to interact with the firmware running on the memory > device. The flow is proven with one implemented command, "identify". > Because the class code has already told the driver this is a memory > device and the identify command is mandatory. > > CXL devices contain an array of capabilities that describe the > interactions software can have with the device or firmware running on > the device. A CXL compliant device must implement the device status and > the mailbox capability. Additionally, a CXL compliant memory device must > implement the memory device capability. Each of the capabilities can > [will] provide an offset within the MMIO region for interacting with the > CXL device. > > The capabilities tell the driver how to find and map the register space > for CXL Memory Devices. The registers are required to utilize the CXL > spec defined mailbox interface. The spec outlines two mailboxes, primary > and secondary. The secondary mailbox is earmarked for system firmware, > and not handled in this driver. > > Primary mailboxes are capable of generating an interrupt when submitting > a background command. That implementation is saved for a later time. > > Reported-by: Colin Ian King <colin.k...@canonical.com> (coverity) > Reported-by: Dan Carpenter <dan.carpen...@oracle.com> (smatch) > Link: https://www.computeexpresslink.org/download-the-specification > Signed-off-by: Ben Widawsky <ben.widaw...@intel.com> > Reviewed-by: Dan Williams <dan.j.willi...@intel.com> (v2) Looks good to me. Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
