On Thu, Feb 18, 2021 at 07:46:39PM +0100, Borislav Petkov wrote: > Both vendors speculate after a near RET in some way: > > Intel: > > "Unlike near indirect CALL and near indirect JMP, the processor will not > speculatively execute the next sequential instruction after a near RET > unless that instruction is also the target of a jump or is a target in a > branch predictor."
Right, the way I read that means it's not a problem for us here. > AMD: > > "Some AMD processors when they first encounter a branch do not stall > dispatch and use the branches dynamic execution to determine the target. > Therefore, they will speculatively dispatch the sequential instructions > after the branch. This happens for near return instructions where it is > not clear what code may exist sequentially after the return instruction. > This behavior also occurs with jmp/call instructions with indirect > targets. Software should place a LFENCE or another dispatch serializing > instruction after the return or jmp/call indirect instruction to prevent > this sequential speculation." > > The AMD side doesn't really need the LFENCE because it'll do LFENCE; > JMP/CALL <target> due to X86_FEATURE_RETPOLINE_AMD, before it reaches > the RET. It never reached the RET. So all in all, I really don't see why we'd need this. Now, if AMD were to say something like: hey, that retpoline is pretty awesome, we ought to use that instead of an uconditional LFENCE, then sure, but as is, I don't think so.
