We add all the properties necessary to control the interconnect
based on the required rates all the way from consumers to the dram.
The fsl,icc-rate specifies the minimum required rate the consumer needs
in order to operate.
For now, only the fec, usdhc1 and usdhc2 are added as consumers.
Signed-off-by: Abel Vesa <abel.v...@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a64b4bf31f5..43760316052f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1112,6 +1112,9 @@ usdhc1: mmc@30b40000 {
"fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&icc IMX8MQ_ICM_USDHC1 &icc
IMX8MQ_ICS_DRAM>;
+ interconnect-names = "path";
+ fsl,icc-rate = <266666>;
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
@@ -1127,6 +1130,9 @@ usdhc2: mmc@30b50000 {
"fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&icc IMX8MQ_ICM_USDHC2 &icc
IMX8MQ_ICS_DRAM>;
+ interconnect-names = "path";
+ fsl,icc-rate = <266666>;
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
@@ -1169,6 +1175,9 @@ fec1: ethernet@30be0000 {
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&icc IMX8MQ_ICM_ENET &icc
IMX8MQ_ICS_DRAM>;
+ interconnect-names = "path";
+ fsl,icc-rate = <800000>;
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
<&clk IMX8MQ_CLK_ENET1_ROOT>,
<&clk IMX8MQ_CLK_ENET_TIMER>,
--
2.29.2
