On Sat, Feb 20, 2021 at 05:32:30PM +1100, Finn Thain wrote:
> Nope. Interrupt priority masking is there to place an upper bound
> interrupt latency. That's why this feature is shipping in contemporary
> hardware (e.g. ARM GIC). If you care about real time workloads on arm64,
> that may interest you.
I don't know if it's still true today, but in the past there was a very
noticeable difference in timer stability between the 68k macintosh
models with the timer interrupt at IPL 1 as compared to the models
where the timer interrupt was at IPL 6. The ability to preempt the
other interrupt handlers made the difference between a usable clock
and one that was pretty unreliable.
Brad Boyer
[email protected]
