From: Richard Fitzgerald <[email protected]>

There must be a delay of at least 150us after writing SCLK_PRESENT
before issuing another I2C write.

This is done using struct reg_sequence because it can specify a delay
after the write and the whole sequence is written atomically.

Signed-off-by: Richard Fitzgerald <[email protected]>
---
 sound/soc/codecs/cs42l42.c | 28 +++++++++++++++++++++++-----
 sound/soc/codecs/cs42l42.h |  1 +
 2 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 7898a2d52a3b7..5755f8baddbcf 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -517,6 +517,24 @@ static const struct snd_soc_dapm_route cs42l42_audio_map[] 
= {
        { "SDOUT2", NULL, "ASP TX EN" },
 };
 
+/* Switch to SCLK. Atomic delay after the write to allow the switch to 
complete. */
+static const struct reg_sequence cs42l42_to_sclk_seq[] = {
+       {
+               .reg = CS42L42_OSC_SWITCH,
+               .def = CS42L42_SCLK_PRESENT_MASK,
+               .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
+       },
+};
+
+/* Switch to OSC. Atomic delay after the write to allow the switch to 
complete. */
+static const struct reg_sequence cs42l42_to_osc_seq[] = {
+       {
+               .reg = CS42L42_OSC_SWITCH,
+               .def = 0,
+               .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
+       },
+};
+
 struct cs42l42_pll_params {
        u32 sclk;
        u8 mclk_div;
@@ -809,6 +827,7 @@ static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 {
        struct snd_soc_component *component = dai->component;
+       struct cs42l42_private *cs42l42 = 
snd_soc_component_get_drvdata(component);
        unsigned int regval;
        u8 fullScaleVol;
 
@@ -828,8 +847,8 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int 
mute, int stream)
                         * SCLK must remain running until after this clock 
switch.
                         * Without a source of clock the I2C bus doesn't work.
                         */
-                       snd_soc_component_update_bits(component, 
CS42L42_OSC_SWITCH,
-                                                     
CS42L42_SCLK_PRESENT_MASK, 0);
+                       regmap_multi_reg_write(cs42l42->regmap, 
cs42l42_to_osc_seq,
+                                              ARRAY_SIZE(cs42l42_to_osc_seq));
                        snd_soc_component_update_bits(component, 
CS42L42_PLL_CTL1,
                                                      CS42L42_PLL_START_MASK, 
0);
                }
@@ -840,9 +859,8 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int 
mute, int stream)
                                                      CS42L42_PLL_START_MASK, 
1);
 
                        /* Mark SCLK as present, turn off internal oscillator */
-                       snd_soc_component_update_bits(component, 
CS42L42_OSC_SWITCH,
-                                                     CS42L42_SCLK_PRESENT_MASK,
-                                                     
CS42L42_SCLK_PRESENT_MASK);
+                       regmap_multi_reg_write(cs42l42->regmap, 
cs42l42_to_sclk_seq,
+                                              ARRAY_SIZE(cs42l42_to_sclk_seq));
                }
                cs42l42->stream_use |= 1 << stream;
 
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h
index 1df9577e367c1..a0c87f2326e69 100644
--- a/sound/soc/codecs/cs42l42.h
+++ b/sound/soc/codecs/cs42l42.h
@@ -755,6 +755,7 @@
 
 #define CS42L42_NUM_SUPPLIES   5
 #define CS42L42_BOOT_TIME_US   3000
+#define CS42L42_CLOCK_SWITCH_DELAY_US 150
 
 static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
        "VA",
-- 
2.30.1

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