On 03/02, Masami Hiramatsu wrote: > > > Not sure I understand you correctly, I know almost nothing about low-level > > x86 magic. > > x86 has normal interrupt and NMI. When an NMI occurs the CPU masks NMI > (the mask itself is hidden status) and IRET releases the mask. The problem > is that if an INT3 is hit in the NMI handler and does a single-stepping, > it has to use IRET for atomically setting TF and return.
Ah, thanks a lot, Oleg.