The crypto mediatek driver has been replaced by the inside-secure driver now. Remove DT bindings documentation and update crypto engine nodes to the mt7623.dtsi files.
Signed-off-by: Vic Wu <vic...@mediatek.com> Acked-by: Ryder Lee <ryder....@mediatek.com> --- Documentation/devicetree/bindings/crypto/mediatek-crypto.txt | 25 ------------------- arch/arm/boot/dts/mt7623.dtsi | 8 +++--- 2 files changed, 3 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/crypto/mediatek-crypto.txt diff --git a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt b/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt deleted file mode 100644 index 450da3661cad..000000000000 --- a/Documentation/devicetree/bindings/crypto/mediatek-crypto.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek cryptographic accelerators - -Required properties: -- compatible: Should be "mediatek,eip97-crypto" -- reg: Address and length of the register set for the device -- interrupts: Should contain the five crypto engines interrupts in numeric - order. These are global system and four descriptor rings. -- clocks: the clock used by the core -- clock-names: Must contain "cryp". -- power-domains: Must contain a reference to the PM domain. - - -Example: - crypto: crypto@1b240000 { - compatible = "mediatek,eip97-crypto"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "cryp"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - }; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index aea6809500d7..25e3f3b04123 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -949,16 +949,14 @@ }; crypto: crypto@1b240000 { - compatible = "mediatek,eip97-crypto"; + compatible = "inside-secure,safexcel-eip97"; reg = <0 0x1b240000 0 0x20000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; + <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; clocks = <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "cryp"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; status = "disabled"; }; -- 2.18.0