The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     afbef30149587ad46f4780b1e0cc5e219745ce90
Gitweb:        
https://git.kernel.org/tip/afbef30149587ad46f4780b1e0cc5e219745ce90
Author:        Kan Liang <kan.li...@linux.intel.com>
AuthorDate:    Mon, 30 Nov 2020 11:38:41 -08:00
Committer:     Ingo Molnar <mi...@kernel.org>
CommitterDate: Sat, 06 Mar 2021 12:52:44 +01:00

perf/x86/intel: Set PERF_ATTACH_SCHED_CB for large PEBS and LBR

To supply a PID/TID for large PEBS, it requires flushing the PEBS buffer
in a context switch.

For normal LBRs, a context switch can flip the address space and LBR
entries are not tagged with an identifier, we need to wipe the LBR, even
for per-cpu events.

For LBR callstack, save/restore the stack is required during a context
switch.

Set PERF_ATTACH_SCHED_CB for the event with large PEBS & LBR.

Fixes: 9c964efa4330 ("perf/x86/intel: Drain the PEBS buffer during context 
switches")
Signed-off-by: Kan Liang <kan.li...@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <pet...@infradead.org>
Signed-off-by: Ingo Molnar <mi...@kernel.org>
Link: https://lkml.kernel.org/r/20201130193842.10569-2-kan.li...@linux.intel.com
---
 arch/x86/events/intel/core.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 5bac48d..7bbb5bb 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3662,8 +3662,10 @@ static int intel_pmu_hw_config(struct perf_event *event)
                if (!(event->attr.freq || (event->attr.wakeup_events && 
!event->attr.watermark))) {
                        event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
                        if (!(event->attr.sample_type &
-                             ~intel_pmu_large_pebs_flags(event)))
+                             ~intel_pmu_large_pebs_flags(event))) {
                                event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
+                               event->attach_state |= PERF_ATTACH_SCHED_CB;
+                       }
                }
                if (x86_pmu.pebs_aliases)
                        x86_pmu.pebs_aliases(event);
@@ -3676,6 +3678,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
                ret = intel_pmu_setup_lbr_filter(event);
                if (ret)
                        return ret;
+               event->attach_state |= PERF_ATTACH_SCHED_CB;
 
                /*
                 * BTS is set up earlier in this path, so don't account twice

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