+ Abel
On Thu, Feb 18, 2021 at 03:29:34PM +0800, Richard Zhu wrote: > The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock, > Change the sys2_pll_500m to sys2_pll_50m. > > Signed-off-by: Richard Zhu <hongxing....@nxp.com> > --- > drivers/clk/imx/clk-imx8mq.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 4dd4ae9d022b..93480d8858be 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -118,7 +118,7 @@ static const char * const imx8mq_pcie1_ctrl_sels[] = > {"osc_25m", "sys2_pll_250m" > static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", > "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", > "clk_ext3", "clk_ext4", }; > > -static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", > "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out", > +static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", > "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out", > "sys2_pll_100m", "sys1_pll_80m", > "sys1_pll_160m", "sys1_pll_200m", }; > > static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", > "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", > "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", }; > -- > 2.17.1 >