[PATCH 1/3] net: dsa: mt7530: remove redundant clock enables

[Ilya Lipnitskiy]

In RGMII mode, the REG_GSWCK_EN bit of CORE_TRGMII_GSW_CLK_CG gets
set three times in a row. In TRGMII mode, two times. Simplify the code
and only set it once for both modes.

Signed-off-by: Ilya Lipnitskiy <ilya.lipnits...@gmail.com>
---
 drivers/net/dsa/mt7530.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index f06f5fa2f898..e785f80f966b 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -461,12 +461,9 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, 
phy_interface_t interface)
                           RG_GSWPLL_POSDIV_200M(2) |
                           RG_GSWPLL_FBKDIV_200M(32));
 
-               /* Enable MT7530 core clock */
-               core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
        }
 
        /* Setup the MT7530 TRGMII Tx Clock */
-       core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
        core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
        core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
        core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
@@ -480,6 +477,8 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t 
interface)
        core_write(priv, CORE_PLL_GROUP7,
                   RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
                   RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
+
+       /* Enable MT7530 core and TRGMII Tx clocks */
        core_set(priv, CORE_TRGMII_GSW_CLK_CG,
                 REG_GSWCK_EN | REG_TRGMIICK_EN);
 
-- 
2.30.1