Arjan van de Ven wrote:
On Sun, 13 Jan 2008 22:29:23 -0500
Tony Camuso <[EMAIL PROTECTED]> wrote:
. There is no need to provide different PCI config access
mechanisms at device granularity, since the PCI config access
mechanism between the CPU and the Northbridge is opaque to
the devices. PCI config mechanisms only need to differ at
the Northbridge level.
This ignores the "lets make it not matter for the 99% of the users" case.
I don't understand. If we're going to differentiate MMCONFIG from some other
access mechanism, it only needs to be done at the Northbridge level. Devices
are electrically ignorant of the protocol used between CPU and Northbridge
to get the Northbridge to assert config cycles on the bus.
. If the system is capable of conf1, then PCI config access
at offsets < 256 should be confined to conf1. This solution
is most effective for existing and legacy systems.
not "conf1" but "what the platform thinks is the best method for < 256".
We have this nice abstraction for the platform to select the best method... we
should use it.
Agreed.
So we have Loic and Ivan's patch limiting MMCONFIG accesses to
offsets >= 256.
And we have Matthew's patch that abstracts the method for config
accesses to offsets < 256.
I beleive Matthew has already tested these patches for functionality
on x86. All that's needed is to test for regressions on other arches.
Is there any interest in providing the following?
1. The ability to use MMCONFIG for all accesses on systems that have
no problems with MMCONFIG.
2. For systems using both PCI and PCI express, testing each bus
for MMCONFIG compliance, to determine whether MMCONFIG can be
used for all config accesses or whether the bus must be limited
all to the method abstracted for offsets < 256.
Or does that introduce unnecessary complications?
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