> -----Original Message----- > From: Kishon Vijay Abraham I <[email protected]> > Sent: Wednesday, March 10, 2021 9:16 PM > To: Kishon Vijay Abraham I <[email protected]>; Vinod Koul > <[email protected]>; Rob Herring <[email protected]>; Philipp Zabel > <[email protected]>; Swapnil Kashinath Jakhade > <[email protected]> > Cc: [email protected]; [email protected]; Lokesh Vutla > <[email protected]> > Subject: [PATCH v6 09/13] phy: cadence: cadence-sierra: Add array of input > clocks in "struct cdns_sierra_phy" > > EXTERNAL MAIL > > > Instead of having separate structure members for each input clock, add > an array for the input clocks within "struct cdns_sierra_phy". This is > in preparation for adding more input clocks required for supporting > additional clock combination. > > Signed-off-by: Kishon Vijay Abraham I <[email protected]> > --- > drivers/phy/cadence/phy-cadence-sierra.c | 25 ++++++++++++++---------- > 1 file changed, 15 insertions(+), 10 deletions(-) > Reviewed-by: Swapnil Jakhade <[email protected]> Thanks & regards, Swapnil > diff --git a/drivers/phy/cadence/phy-cadence-sierra.c > b/drivers/phy/cadence/phy-cadence-sierra.c > index 44c52a0842dc..a45278c30948 100644 > --- a/drivers/phy/cadence/phy-cadence-sierra.c > +++ b/drivers/phy/cadence/phy-cadence-sierra.c > @@ -144,6 +144,13 @@ > #define SIERRA_MAX_LANES 16 > #define PLL_LOCK_TIME 100000 > > +#define CDNS_SIERRA_INPUT_CLOCKS 3 > +enum cdns_sierra_clock_input { > + PHY_CLK, > + CMN_REFCLK_DIG_DIV, > + CMN_REFCLK1_DIG_DIV, > +}; > + > static const struct reg_field macro_id_type = > REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); > static const struct reg_field phy_pll_cfg_1 = > @@ -197,9 +204,7 @@ struct cdns_sierra_phy { > struct regmap_field *macro_id_type; > struct regmap_field *phy_pll_cfg_1; > struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; > - struct clk *clk; > - struct clk *cmn_refclk_dig_div; > - struct clk *cmn_refclk1_dig_div; > + struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; > int nsubnodes; > u32 num_lanes; > bool autoconf; > @@ -281,8 +286,8 @@ static int cdns_sierra_phy_init(struct phy *gphy) > if (phy->autoconf) > return 0; > > - clk_set_rate(phy->cmn_refclk_dig_div, 25000000); > - clk_set_rate(phy->cmn_refclk1_dig_div, 25000000); > + clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); > + clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); > if (ins->phy_type == PHY_TYPE_PCIE) { > num_cmn_regs = phy->init_data->pcie_cmn_regs; > num_ln_regs = phy->init_data->pcie_ln_regs; > @@ -488,7 +493,7 @@ static int cdns_sierra_phy_get_clocks(struct > cdns_sierra_phy *sp, > dev_err(dev, "failed to get clock phy_clk\n"); > return PTR_ERR(clk); > } > - sp->clk = clk; > + sp->input_clks[PHY_CLK] = clk; > > clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); > if (IS_ERR(clk)) { > @@ -496,7 +501,7 @@ static int cdns_sierra_phy_get_clocks(struct > cdns_sierra_phy *sp, > ret = PTR_ERR(clk); > return ret; > } > - sp->cmn_refclk_dig_div = clk; > + sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; > > clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); > if (IS_ERR(clk)) { > @@ -504,7 +509,7 @@ static int cdns_sierra_phy_get_clocks(struct > cdns_sierra_phy *sp, > ret = PTR_ERR(clk); > return ret; > } > - sp->cmn_refclk1_dig_div = clk; > + sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; > > return 0; > } > @@ -585,7 +590,7 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > if (ret) > return ret; > > - ret = clk_prepare_enable(sp->clk); > + ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); > if (ret) > return ret; > > @@ -662,7 +667,7 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > reset_control_put(sp->phys[i].lnk_rst); > of_node_put(child); > clk_disable: > - clk_disable_unprepare(sp->clk); > + clk_disable_unprepare(sp->input_clks[PHY_CLK]); > reset_control_assert(sp->apb_rst); > return ret; > } > -- > 2.17.1
