On 3/15/21 11:26 AM, Michael Walle wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Am 2021-03-15 09:26, schrieb tudor.amba...@microchip.com: >> On 3/6/21 2:05 AM, Michael Walle wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know >>> the content is safe >>> >>> With all the helper functions in place, add OTP support for the >>> Winbond >>> W25Q32JW and W25Q32FW. >>> >>> Both were tested on a LS1028A SoC with a NXP FSPI controller. >>> >>> Signed-off-by: Michael Walle <mich...@walle.cc> >>> --- >>> drivers/mtd/spi-nor/winbond.c | 17 +++++++++++++++-- >>> 1 file changed, 15 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/mtd/spi-nor/winbond.c >>> b/drivers/mtd/spi-nor/winbond.c >>> index e5dfa786f190..9a3f8ff007fd 100644 >>> --- a/drivers/mtd/spi-nor/winbond.c >>> +++ b/drivers/mtd/spi-nor/winbond.c >>> @@ -55,14 +55,18 @@ static const struct flash_info winbond_parts[] = { >>> { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, >>> { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, >>> SECT_4K | SPI_NOR_DUAL_READ | >>> SPI_NOR_QUAD_READ | >>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, >>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) >>> + OTP_INFO(256, 3, 0x1000, 0x1000) >>> + }, >>> + >>> { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64, >>> SECT_4K | SPI_NOR_DUAL_READ | >>> SPI_NOR_QUAD_READ | >>> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) >>> }, >>> { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64, >>> SECT_4K | SPI_NOR_DUAL_READ | >>> SPI_NOR_QUAD_READ | >>> - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, >>> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) >>> + OTP_INFO(256, 3, 0x1000, 0x1000) }, >>> { "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128, >>> SECT_4K | SPI_NOR_DUAL_READ | >>> SPI_NOR_QUAD_READ | >>> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, >>> @@ -131,9 +135,18 @@ static int winbond_set_4byte_addr_mode(struct >>> spi_nor *nor, bool enable) >>> return spi_nor_write_disable(nor); >>> } >>> >>> +static const struct spi_nor_otp_ops winbond_otp_ops = { >>> + .read = spi_nor_otp_read_secr, >>> + .write = spi_nor_otp_write_secr, >>> + .lock = spi_nor_otp_lock_sr2, >>> + .is_locked = spi_nor_otp_is_locked_sr2, >>> +}; >> >> Should we have this in otp.c? It can be shared with gigadevice as well >> as far as I understood. > > It should work in principle for both vendors, but I couldn't test it. So > for now, I've kept it private to winbond.c. If there will be OTP support > for other flashes with the same ops, it should be moved. >
Ok.