Hi!
Dne ponedeljek, 15. marec 2021 ob 05:32:49 CET je Samuel Holland napisal(a):
> For a CPU to enter an idle state, there must be some timer which can
> trigger an IRQ to wake it back up. The local ARM architectural timer is
> not sufficient, because that timer stops when the CPU is powered down.
> Some other CPU's ARM architectural timer can be used, but this prevents
> that other CPU from entering an idle state. So to allow all CPUs to
> enter an idle state at the same time, some MMIO timer must be available
> that is not tied to any CPU.
>
> The basic "sun4i" timer seems most appropriate for this purpose due to
> its moderate rate, balancing precision and power consumption.
>
> Signed-off-by: Samuel Holland <sam...@sholland.org>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
> arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++
> 3 files changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index
> 33df866f6ea9..64e8b4a372cc 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -905,6 +905,15 @@ uart4_rts_cts_pins: uart4-rts-cts-pins {
> };
> };
>
> + timer@1c20c00 {
> + compatible = "allwinner,sun50i-a64-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x01c20c00 0xa0>;
> + interrupts = <GIC_SPI 18
IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> wdt0: watchdog@1c20ca0 {
> compatible = "allwinner,sun50i-a64-wdt",
> "allwinner,sun6i-a31-wdt";
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index
> 62334054c710..9ba3b30e11fa 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -332,6 +332,15 @@ cpu_speed_grade: cpu-speed-grade@1c {
> };
> };
>
> + timer@3009000 {
> + compatible = "allwinner,sun50i-h6-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x03009000 0xa0>;
> + interrupts = <GIC_SPI 48
IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 49
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> watchdog: watchdog@30090a0 {
> compatible = "allwinner,sun50i-h6-wdt",
> "allwinner,sun6i-a31-wdt";
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index
> c277b53f94ea..ff55712ce96e 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
This file does not exist yet upstream.
Best regards,
Jernej
> @@ -128,6 +128,15 @@ ccu: clock@3001000 {
> #reset-cells = <1>;
> };
>
> + timer@3009000 {
> + compatible = "allwinner,sun50i-h616-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x03009000 0xa0>;
> + interrupts = <GIC_SPI 48
IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 49
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> watchdog: watchdog@30090a0 {
> compatible = "allwinner,sun50i-h616-wdt",
> "allwinner,sun6i-a31-wdt";
