On Mon, 15 Mar 2021 at 20:39, Douglas Anderson <diand...@chromium.org> wrote: > > As per Dmitry Baryshkov [1]: > a) The 2nd "reg" should be 0x3c because "Offset 0x38 is > USB3_DP_COM_REVISION_ID3 (not used by the current driver though)." > b) The 3rd "reg" "is a serdes region and qmp_v3_dp_serdes_tbl contains > registers 0x148 and 0x154." > > I think because the 3rd "reg" is a serdes region we should just use > the same size as the 1st "reg"?
Yes, this looks logical to me. Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org> > > [1] https://lore.kernel.org/r/ee5695bb-a603-0dd5-7a7f-695e919b1...@linaro.org > > Cc: Stephen Boyd <swb...@chromium.org> > Cc: Jeykumar Sankaran <jsa...@codeaurora.org> > Cc: Chandan Uddaraju <chand...@codeaurora.org> > Cc: Vara Reddy <va...@codeaurora.org> > Cc: Tanmay Shah <tan...@codeaurora.org> > Cc: Rob Clark <robdcl...@chromium.org> > Fixes: 58fd7ae621e7 ("arm64: dts: qcom: sc7180: Update dts for DP phy inside > QMP phy") > Reported-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org> > Signed-off-by: Douglas Anderson <diand...@chromium.org> > --- > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi > b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 83fbb481cae5..61732e5efe62 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -2754,8 +2754,8 @@ usb_1_hsphy: phy@88e3000 { > usb_1_qmpphy: phy-wrapper@88e9000 { > compatible = "qcom,sc7180-qmp-usb3-dp-phy"; > reg = <0 0x088e9000 0 0x18c>, > - <0 0x088e8000 0 0x38>, > - <0 0x088ea000 0 0x40>; > + <0 0x088e8000 0 0x3c>, > + <0 0x088ea000 0 0x18c>; > status = "disabled"; > #address-cells = <2>; > #size-cells = <2>; -- With best wishes Dmitry
