15.03.2021 21:39, Dmitry Osipenko пишет: >>> + /* >>> + * Horizontal downscale needs a lower memory latency, which roughly >>> + * depends on the scaled width. Trying to tune latency of a memory >>> + * client alone will likely result in a strong negative impact on >>> + * other memory clients, hence we will request a higher bandwidth >>> + * since latency depends on bandwidth. This allows to prevent memory >>> + * FIFO underflows for a large plane downscales, meanwhile allowing >>> + * display to share bandwidth fairly with other memory clients. >>> + */ >>> + if (src_w > dst_w) >>> + mul = (src_w - dst_w) * bpp / 2048 + 1; >>> + else >>> + mul = 1; >> [...] >> >> One point is unexplained yet: why is the multiplier proportional to a >> *difference* between src and dst widths? Also, I would expect max (worst >> case) is pixclock * read_size when src_w/dst_w >= read_size. > IIRC, the difference gives a more adequate/practical result than the > proportion. Although, downstream driver uses proportion. I'll try to > revisit this for the next version of the patch.
I tried to re-test everything and can't reproduce problems that existed previously. We didn't have a finished memory drivers back then and I think that Tegra30 latency tuning support and various Tegra20 changes fixed those problems. I'll remove this hunk in the next version.
