The following commit has been merged into the x86/cpu branch of tip: Commit-ID: a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab Gitweb: https://git.kernel.org/tip/a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab Author: Tony Luck <[email protected]> AuthorDate: Fri, 19 Mar 2021 10:39:19 -07:00 Committer: Ingo Molnar <[email protected]> CommitterDate: Sat, 20 Mar 2021 12:12:10 +01:00
x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN New CPU model, same MSRs to control and read the inventory number. Signed-off-by: Tony Luck <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected] --- arch/x86/kernel/cpu/mce/intel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index e309476..acfd5d9 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM:
