Fixes the following W=1 kernel build warning(s):
../arch/x86/kernel/cpu/intel.c: In function ‘init_intel’:
../arch/x86/kernel/cpu/intel.c:644:20: warning: variable ‘l2’ set but not used
[-Wunused-but-set-variable]
unsigned int l1, l2;
^~
Compilation command(s):
make allmodconfig ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-
make W=1 arch/x86/kernel/cpu/intel.o ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-
According to Intel Software Developer's Manual Table 2-2 through Table 2-24
about MSRs:
X86_FEATURE_BTS which represents Branch Trace Storage Unavailable and
X86_FEATURE_PEBS
represens Processor Event Based Sampling (PEBS) Unavailable, but on some
platform these fields
maybe reserved or not available. For the function init_intel it self, only bit
11 and bit 12
are used for checking BTS and PEBS, and higher 32 bits are not used. So cast to
void to
avoid warning.
Reported-by: Hulk Robot <hul...@huawei.com>
Signed-off-by: Xu Yihang <xuyih...@huawei.com>
---
arch/x86/kernel/cpu/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 63e381a46153..547ba6668eb3 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -644,6 +644,7 @@ static void init_intel(struct cpuinfo_x86 *c)
unsigned int l1, l2;
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+ (void) l2;
if (!(l1 & (1<<11)))
set_cpu_cap(c, X86_FEATURE_BTS);
if (!(l1 & (1<<12)))
--
2.17.1
