Quoting Maulik Shah (2021-03-22 03:30:15)
> -- qcom,pdc-ranges:
> - Usage: required
> - Value type: <u32 array>
> - Definition: Specifies the PDC pin offset and the number of PDC ports.
> - The tuples indicates the valid mapping of valid PDC ports
> - and their hwirq mapping.
> - The first element of the tuple is the starting PDC port.
> - The second element is the GIC hwirq number for the PDC
> port.
> - The third element is the number of interrupts in sequence.
> -
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> new file mode 100644
> index 0000000..8b4151c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. PDC interrupt controller
> +
> +maintainers:
> + - Maulik Shah <[email protected]>
> +
> +description: |
> + Qualcomm Technologies, Inc. SoCs based on the RPM Hardened architecture
> have a
> + Power Domain Controller (PDC) that is on always-on domain. In addition to
> + providing power control for the power domains, the hardware also has an
> + interrupt controller that can be used to help detect edge low interrupts as
> + well detect interrupts when the GIC is non-operational.
> +
> + GIC is parent interrupt controller at the highest level. Platform interrupt
> + controller PDC is next in hierarchy, followed by others. Drivers requiring
> + wakeup capabilities of their device interrupts routed through the PDC, must
> + specify PDC as their interrupt controller and request the PDC port
> associated
> + with the GIC interrupt. See example below.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + # Should contain "qcom,<soc>-pdc" and "qcom,pdc"
> + - qcom,sc7180-pdc #For SC7180
> + - qcom,sc7280-pdc #For SC7280
> + - qcom,sdm845-pdc #For SDM845
> + - qcom,sm8250-pdc #For SM8250
> + - qcom,sm8350-pdc #For SM8350
> + - const: qcom,pdc
> +
> + reg:
> + description: |
> + Specifies the base physical address for PDC hardware followed by
> optional
> + PDC's GIC interface registers that need to be configured for wakeup
> capable
> + GPIOs routed to the PDC.
> + minItems: 1
> + maxItems: 2
Can this be
items:
- description: base registers
- description: wakeup configuration registers
and then we should always have both registers?
> +
> + '#interrupt-cells':
> + # Specifies the number of cells needed to encode an interrupt.
> + # The first element of the tuple is the PDC pin for the interrupt.
> + # The second element is the trigger type.
> + const: 2
> +
> + interrupt-controller: true
> +
> + qcom,pdc-ranges:
> + description: |
> + Specifies the PDC pin offset and the number of PDC ports.
> + The tuples indicates the valid mapping of valid PDC ports
> + and their hwirq mapping.
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + items:
> + items:
> + - description: |
> + "a" The first element of the tuple is the starting PDC port.
> + - description: |
> + "b" The second element is the GIC SPI number for the PDC port.
> + - description: |
> + "c" The third element is the number of interrupts in sequence.
Do we need the "a", "b", "c" prefixes? Is there any minItems or maxItems
that can be placed on this?
> +
> +required:
> + - compatible
> + - reg
> + - '#interrupt-cells'
> + - interrupt-controller
> + - qcom,pdc-ranges
> +
> +additionalProperties: false
