On Wed, Mar 24, 2021 at 11:44:12AM -0500, Brijesh Singh wrote: > Add CPU feature detection for Secure Encrypted Virtualization with > Secure Nested Paging. This feature adds a strong memory integrity > protection to help prevent malicious hypervisor-based attacks like > data replay, memory re-mapping, and more. > > Cc: Thomas Gleixner <t...@linutronix.de> > Cc: Ingo Molnar <mi...@redhat.com> > Cc: Borislav Petkov <b...@alien8.de> > Cc: Joerg Roedel <jroe...@suse.de> > Cc: "H. Peter Anvin" <h...@zytor.com> > Cc: Tony Luck <tony.l...@intel.com> > Cc: Dave Hansen <dave.han...@intel.com> > Cc: "Peter Zijlstra (Intel)" <pet...@infradead.org> > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Tom Lendacky <thomas.lenda...@amd.com> > Cc: David Rientjes <rient...@google.com> > Cc: Sean Christopherson <sea...@google.com> > Cc: x...@kernel.org > Cc: k...@vger.kernel.org > Signed-off-by: Brijesh Singh <brijesh.si...@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/amd.c | 3 ++- > arch/x86/kernel/cpu/scattered.c | 1 + > 3 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index 84b887825f12..a5b369f10bcd 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -238,6 +238,7 @@ > #define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers > VMMCALL hypercall instruction */ > #define X86_FEATURE_SEV_ES ( 8*32+20) /* AMD Secure Encrypted > Virtualization - Encrypted State */ > #define X86_FEATURE_VM_PAGE_FLUSH ( 8*32+21) /* "" VM Page Flush MSR is > supported */ > +#define X86_FEATURE_SEV_SNP ( 8*32+22) /* AMD Secure Encrypted > Virtualization - Secure Nested Paging */
That leaf got a separate word now: word 19. For the future: pls redo your patches against tip/master because it has the latest state of affairs in tip-land. > /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ > #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, > RDGSBASE, WRGSBASE instructions*/ > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > index f8ca66f3d861..39f7a4b5b04c 100644 > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -586,7 +586,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 > *c) > * If BIOS has not enabled SME then don't advertise the > * SME feature (set in scattered.c). > * For SEV: If BIOS has not enabled SEV then don't advertise the > - * SEV and SEV_ES feature (set in scattered.c). > + * SEV, SEV_ES and SEV_SNP feature (set in scattered.c). So you can remove the "scattered.c" references in the comments here. > * > * In all cases, since support for SME and SEV requires long mode, > * don't advertise the feature under CONFIG_X86_32. > @@ -618,6 +618,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 > *c) > clear_sev: > setup_clear_cpu_cap(X86_FEATURE_SEV); > setup_clear_cpu_cap(X86_FEATURE_SEV_ES); > + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); > } > } > > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index 236924930bf0..eaec1278dc2e 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_SEV_ES, CPUID_EAX, 3, 0x8000001f, 0 }, > { X86_FEATURE_SME_COHERENT, CPUID_EAX, 10, 0x8000001f, 0 }, > { X86_FEATURE_VM_PAGE_FLUSH, CPUID_EAX, 2, 0x8000001f, 0 }, > + { X86_FEATURE_SEV_SNP, CPUID_EAX, 4, 0x8000001f, 0 }, > { 0, 0, 0, 0, 0 } > }; And this too. Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette