On Thu, 25 Mar 2021 18:44:48 +0000,
Thomas Gleixner <t...@linutronix.de> wrote:
>
> On Thu, Mar 25 2021 at 17:08, Marc Zyngier wrote:
> > Megha Dey <megha....@intel.com> wrote:
> >> @@ -434,6 +434,12 @@ int __msi_domain_alloc_irqs(struct irq_domain
> >> *domain, struct device *dev,
> >> if (ret)
> >> return ret;
> >>
> >> + if (ops->msi_alloc_store) {
> >> + ret = ops->msi_alloc_store(domain, dev, nvec);
> >
> > What is supposed to happen if we get aliasing devices (similar to what
> > we have with devices behind a PCI bridge)?
> >
> > The ITS code goes through all kind of hoops to try and detect this
> > case when sizing the translation tables (in the .prepare callback),
> > and I have the feeling that sizing the message store is analogous.
>
> No. The message store itself is sized upfront by the underlying 'master'
> device. Each 'master' device has it's own irqdomain.
>
> This is the allocation for the subdevice and this is not part of PCI and
> therefore not subject to PCI aliasing.
Fair enough. If we are guaranteed that there is no aliasing, then this
point is moot.
M.
--
Without deviation from the norm, progress is not possible.
