> -----Original Message-----
> From: Andrew Lunn <and...@lunn.ch>
> Sent: Monday, 5 April, 2021 9:11 PM
> To: Sit, Michael Wei Hong <michael.wei.hong....@intel.com>
> Cc: peppe.cavall...@st.com; alexandre.tor...@st.com;
> joab...@synopsys.com; da...@davemloft.net;
> k...@kernel.org; mcoquelin.st...@gmail.com;
> li...@armlinux.org.uk; Voon, Weifeng
> <weifeng.v...@intel.com>; Ong, Boon Leong
> <boon.leong....@intel.com>; qiangqing.zh...@nxp.com; Wong,
> Vee Khee <vee.khee.w...@intel.com>; fugang.d...@nxp.com;
> Chuah, Kim Tatt <kim.tatt.ch...@intel.com>;
> net...@vger.kernel.org; linux-stm32@st-md-
> mailman.stormreply.com; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; hkallwe...@gmail.com
> Subject: Re: [PATCH net-next v2 0/2] Enable 2.5Gbps speed for
> stmmac
>
> On Mon, Apr 05, 2021 at 07:29:51PM +0800, Michael Sit Wei Hong
> wrote:
> > This patchset enables 2.5Gbps speed mode for stmmac.
> > Link speed mode is detected and configured at serdes power
> up sequence.
> > For 2.5G, we do not use SGMII in-band AN, we check the link
> speed mode
> > in the serdes and disable the in-band AN accordingly.
> >
> > Changes:
> > v1 -> v2
> > patch 1/2
> > -Remove MAC supported link speed masking
> >
> > patch 2/2
> > -Add supported link speed masking in the PCS
>
> So there still some confusion here.
>
> ------------ --------
> |MAC - PCS |---serdes---| PHY |--- copper
> ------------ --------
>
>
> You have a MAC and an PCS in the stmmac IP block. That then has
> some
> sort of SERDES interface, running 1000BaseX, SGMII, SGMII
> overclocked
> at 2.5G or 25000BaseX. Connected to the SERDES you have a PHY
> which
> converts to copper, giving you 2500BaseT.
>
> You said earlier, that the PHY can only do 2500BaseT. So it should
> be
> the PHY driver which sets supported to 2500BaseT and no other
> speeds.
>
> You should think about when somebody uses this MAC with a
> different
> PHY, one that can do the full range of 10/half through to 2.5G
> full. What generally happens is that the PHY performs auto-neg to
> determine the link speed. For 10M-1G speeds the PHY will
> configure its
> SERDES interface to SGMII and phylink will ask the PCS to also be
> configured to SGMII. If the PHY negotiates 2500BaseT, it will
> configure its side of the SERDES to 2500BaseX or SGMII
> overclocked at
> 2.5G. Again, phylink will ask the PCS to match what the PHY is
> doing.
>
> So, where exactly is the limitation in your hardware? PCS or PHY?
The limitation in the hardware is at the PCS side where it is either running
in SGMII 2.5G or SGMII 1G speeds.
When running on SGMII 2.5G speeds, we disable the in-band AN and use 2.5G speed
only
>
> Andrew
