On Tue, 2021-04-06 at 21:48 +0200, Wolfram Sang wrote: > On Sat, Mar 13, 2021 at 04:04:24PM +0800, qii.w...@mediatek.com wrote: > > From: Qii Wang <qii.w...@mediatek.com> > > > > tSU,STA/tHD,STA/tSU,STOP maybe out of spec due to device > > clock-stretching or circuit loss, we could get device > > clock-stretch time from dts to adjust these parameters > > to meet the spec via EXT_CONF register. > > > > Signed-off-by: Qii Wang <qii.w...@mediatek.com> > > I tried to understand from the code what the new binding expresses, but > I don't fully understand it. Is it the maximum clock stretch time? > Because I cannot recall a device which always uses the same delay for > clock stretching. >
Due to clock stretch, our HW IP cannot meet the ac-timing spec(tSU;STA,tSU;STO). There isn't a same delay for clock stretching, so we need pass a parameter which can be found through measurement to meet most conditions.
